1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors having strained channel regions by using embedded silicon/germanium (Si/Ge) so as to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element for complex circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions so as to provide low sheet and contact resistivity in combination with desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for maintaining high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby enabling a performance improvement that is comparable with the advance to a technology standard requiring extremely scaled critical dimensions, while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium material next to the channel region so as to induce a compressive stress that may result in a corresponding strain. When forming the Si/Ge material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Although the technique has significant advantages in view of performance gain of P-channel transistors and thus of the entire CMOS device, it turns out, however, that, in advanced semiconductor devices including a large number of transistor elements, an increased variability of device performance may be observed, which may be associated with the above-described technique for incorporating a strained silicon/germanium alloy in the drain and source regions of P-channel transistors.
The presence of a strain-inducing silicon/germanium material in the drain and source regions of P-channel transistors may drastically alter the current drive capability of the transistor and, thus, even small variations during the incorporation of the silicon/germanium material or any variations of the material composition may, therefore, significantly affect performance of the P-channel transistor. The strain-inducing effect of the embedded silicon/germanium material depends on the amount of the embedded strain-inducing semiconductor material, the distance with respect to the channel region and also depends on the size and shape of the strain-inducing semiconductor material. For example, incorporating an increased fraction of germanium may result in an increase of the resulting strain, since the corresponding lattice mismatch between the silicon/germanium material and the silicon material of the active region may be increased. The maximum concentration of germanium in the semiconductor alloy, however, may depend on the process strategy used, since further increasing the germanium concentration may result in undue germanium agglomeration, which in turn may provide increased lattice defects and the like. Furthermore, the amount of the strain-inducing material and the shape thereof in the drain and source regions may depend on the size and shape of the cavities formed in the drain and source areas, wherein the effective distance from the channel region may also be substantially determined on the basis of the size and shape of the corresponding cavities. Consequently, for a given deposition recipe of providing the strain-inducing silicon/germanium material, i.e., for a given germanium concentration in the semiconductor material, the size and shape of the cavities may play an important role in adjusting the overall performance of the transistor, wherein, in particular, across-die uniformity and across-substrate uniformity of the resulting performance gain of P-channel transistors may be significantly determined on the basis of the size and shape of the cavities.
A typical conventional process flow for forming an embedded silicon/germanium material in P-channel transistors may include the following process steps. After forming the active semiconductor regions for forming transistors therein and thereabove, which is typically accomplished by forming appropriate isolation regions that laterally delineate the active regions, the gate electrode structures are formed on the basis of any appropriate process strategy. That is, appropriate materials, such as dielectric materials, electrode materials and the like, are provided in combination with one or more appropriate dielectric cap materials, which may be used, in addition to the actual patterning of the gate layer stack, as etch and deposition masks in a later manufacturing stage, when forming the embedded strain-inducing silicon/germanium material. In sophisticated applications, the gate electrode structures of field effect transistors may be provided with a gate length of 50 nm and less, thereby providing the basic sophisticated transistor performance, for instance in terms of switching speed and drive current capability. The reduced critical dimensions, however, may also contribute to a pronounced dependency of the resulting transistor performance on process variations, in particular when produced upon implementing a very efficient performance-enhancing mechanism, such as embedding the strain-inducing silicon/germanium material in P-channel transistors. For example, a variation of the lateral distance of the silicon/germanium material with respect to the channel region may over-proportionally influence the finally obtained performance, in particular when basically extremely scaled transistors are considered. For example, forming any sidewall spacers on the gate electrode structures for preserving integrity of sensitive materials, such as the gate dielectric material, the electrode material and the like, may significantly influence the lateral distance, wherein all but readily reducing the resulting spacer width may not be compatible with other device requirements, such as integrity of the gate materials. Consequently, in particular for a reduced gate length, even a minute variation of the spacer width may significantly contribute to overall variability of the resulting performance gain obtained by the embedded silicon/germanium material. Based on the dielectric cap material and the sidewall spacer structures, cavities may then be etched into the drain and source areas, wherein the size and shape may be substantially determined on the basis of the etch parameters of the corresponding etch strategy. It should be appreciated that any other transistors, such as N-channel transistors, in which an incorporated silicon/germanium material is not required, are covered by an appropriate mask layer. It is well known that the etch rate in anisotropic plasma assisted processes may depend on the local neighborhood of a certain device area. In plasma assisted anisotropic etch processes, which may be performed on the basis of hydrogen bromide and the like, for etching silicon material, appropriate organic additives are used in order to adjust the anisotropic nature in combination with appropriately selected plasma conditions of the etch process under consideration. The presence of reactive components, organic additives and even the plasma conditions may, however, slightly vary depending on the local conditions, such as the “density” of circuit elements and the like. That is, the local configuration of the semiconductor device may affect the local etch conditions, for instance, in one area, a plurality of exposed surface areas to be etched may be present, while, in other device areas, a significantly reduced “density” of corresponding surface areas may be present, thereby contributing to a different etch behavior in these areas. For example, upon forming cavities in the silicon-based drain and source regions of transistors, in densely packed device areas, i.e., in device areas in which closely spaced gate electrodes of transistors may be present, a different etch behavior occurs compared to less densely packed device areas. A corresponding effect is also well known as “pattern loading,” which may thus result in a difference in size and/or shape of the resulting cavities, which in turn may, therefore, contribute to very pronounced variability of transistor performance, as is also discussed above.
In some conventional approaches, the variability in size and shape of the resulting cavities is compensated for, at least to a certain degree, by additionally performing a wet chemical etch process that has a high crystallographic anisotropy so that precise control of the lateral offset of the cavities and their size and shape may be accomplished. For example, a crystallographically anisotropic etch process may be accomplished by using well-established etch reagents, such as tetra methyl ammonium hydroxide (TMAH), potassium hydroxide and the like, wherein the wet chemical etch chemistry has an inherent “anisotropic” etch behavior with respect to different crystallographic orientations of the silicon material to be patterned. Consequently, this inherent difference in etch rate provides a restricted etch behavior in the lateral direction of the cavities for a standard crystallographic configuration of the silicon-based material, thereby obtaining superior process uniformity with respect to the size and shape of the resulting cavities. Typically, a standard crystallographic orientation of a silicon material is used, i.e., a (100) surface orientation with the transistor length directions oriented along a <110> direction, or any physically equivalent direction, wherein a significantly reduced etch rate along <111> directions is observed compared to other crystallographic axes, such as the <110>, <100> axes or any corresponding equivalent directions. It should be appreciated that, in this application, corresponding crystallographic orientations are to be understood as representing physically equivalent orientations, i.e., a <100> orientation is to be understood as representing any physically equivalent orientations, such as <010>, <001>, <−100> and the like. The same holds true for crystal planes.
Consequently, upon applying a final crystallographically anisotropic etch step, well-defined sidewall surfaces may be formed in the cavity, for instance according to the crystal geometry, wherein the (111) planes may act as “etch stop” layers.
Although this conventional approach may provide superior etch conditions and, thus, a superior shape of the resulting cavities, it, nevertheless, turns out that a significant variation in cavity depth across semiconductor die regions may be observed, wherein a reduced cavity depth is encountered in device areas comprising closely spaced gate electrode structures, while an increased depth can be found in device areas of less densely packed transistors.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.